Performance and reliability of SRAMs in low-voltage operation pose a challenge for the engineering society. One engineering challenge of low-voltage SRAM is mainly due to analog sense-amplifiers which have a degraded performance at a scaled supply voltage. Moreover, the existing low-voltage SRAM solutions comes with a higher area cost as they require 8 transistor in the bitcell, higher design, and fabrication cost.
With the recent uprising of new devices and applications within the Internet of Things (IoT) field, the demand for ultra-low voltage design is increased. Most IoT devices would benefit from a low-voltage memory to save battery, and also from a memory with a reduced production and area cost. The International Technology Roadmap for Semiconductors (ITRS roadmap) states that revolutionary replacements of current 6T SRAM structures are challenges to be researched.
There is thus a need for a high-yield, low-voltage SRAM.